How I learned VHDL

About me

I started my engineering career interest in signal processing. At the same time I enjoyed high performance computing and how to write code to execute as fast as possible. With these two interests I found FPGAs and VHDL.

Why I wanted to learn VHDL

I wanted to learn VHDL because with VHDL you had the ability to "program hardware". As opposed to writing code for an embedded processing with maybe one processing with hardware for one multiply in a clock cycle. Or even if you are writing code for a server based system that has 24 or 48 cores with some complex pipe-lining and cache staging for data you can still run out of hardware to perform a certain task.

My task I was interested in was the signal processing in a communication system. In these systems data can come in very quickly and with the internet hosting copious amounts of data I knew there would be a need for such systems.

How I approached learning VHDL

I think in learning anything it is important to know that you can figure it out. There are always resources for you to try another angle at the problem. I mean there are many places on Google that you can search for anything that you can dream up. Just keep trying.

Another thing that is important to know is that if you don't know how to do something then break it down in to smaller chunks that you can figure out. That is the approach that I took in learning VHDL. There are simulators out there like Vivado Simulator, modelsim, questasim, icraus, and a few other open source solutions for HDL simulation. These tools are important. It helps you look at what you are doing on a clock cycle by clock cycle bases. Having all the information in front of you is important to be able to know where the bugs are and how to fix them.

So many people are excited about getting VHDL working on the FPGA that they want to skip the simulation portion which is a very big mistake because debugging on the FPGA is way more difficult.

Challenges I faced

VHDL is fundamentally different than other programming that you've ever done. Since you are programming configurable hardware you are programming voltages on a wire. Because of this assignment statements in VHDL can occur at the same time in the FPGA. This confused me for a while and only working through problems in the simulator did I finally get a handle on the nuances of the language.

Key takeaways

The biggest takeaway is to keep working at it. VHDL is certainly something you need to keep working at. If you run into issues, which you will, you can use resources at your disposal to figure it out. You can also ask me.

Tips and advice

Always remember it takes a full clock cycle to register a value under a clocked process.

Final thoughts and next steps

Next I am going to learn to interface with external chips. I'll start with the SPI interface.