Principal Architect
Architected high-level compilation flows all the way from C++ to gates.
Architected high-level compilation flows all the way from C++ to gates.
C++
VHDL
SystemVerilog
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C++
VHDL
SystemVerilog
Software architecture
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Sr. Digital Design Engineer
Analog Devices
2019-04-01-2021-08-01
Designed and implemented the MAC sub-system in a 10Mbps industrial Ethernet IC, which incorporates unique, integrated on-chip switch feat...
Designed and implemented the MAC sub-system in a 10Mbps industrial Ethernet IC, which incorporates unique, integrated on-chip switch features. I'm responsible for the design of the block and it's subcomponents and their implementation in SystemVerilog, as well as their integration into the rest of the complex ASIC design.
SystemVerilog
UVM
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SystemVerilog
UVM
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FPGA Design Consultant
Eulambia Advanced Technologies
2018-05-01-2019-10-01
Supported the development of a 5G baseband unit by implementing a JESD204B interface and coupling it with DACs and ADCs from Analog Devic...
Supported the development of a 5G baseband unit by implementing a JESD204B interface and coupling it with DACs and ADCs from Analog Devices to implement various link configurations. This was then coupled to the complete BBU design and tested and verified on an Intel Arria 10 board.
VHDL
FPGA
Embedded Systems
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VHDL
FPGA
Embedded Systems
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