Jatinkumar Koshiya

Verifying custom AI chips for Microsoft Artificial Intelligence team

Worked in memory subsystem division at Unit level verification in GPU. Worked on performance verification at Unit level.

▪ Project: Next Gen IPUs (Intel Infrastructure Processing Unit) (SmartNIC) ▪ Reference model component development for out-of-order packet flit received from AXI4 stream and end to end scoreboard of packets ▪ Experience in leading packet processing IP verification and class of service queue IP verification from testplan development to coverage closure ▪ Single-handed drove TFM (Tool Flow Methodology) related activities at multiple IP. ▪ Developed Perl script for generating directed regression test suite for functional verification of packet processing IP. ▪ Trained multiple interns joined the team with SystemVerilog, UVM methodology and functional verification. ▪ Successfully lead and completed packet processing IP level Unit and features verification from architecture understanding, testplan creation, environment infrastructure update, testbench component development, test scenario and sequence creation, checkers, test running and debugging with designers or at subsystem level, regression, triage and coverage closure ▪ Having experience in networking ethernet protocol and AMBA AXI4, APB communication protocol. ▪ Hands on experience with verification tools such as VCS, Verdi waveform analyzer and third-party VIP integration (such as Synopsys VIPs). ▪ Expertise in constraint random function verification and Performance-QoS verification of multiple IPs in SystemVerilog and UVM based testbench environment