Jatinkumar Koshiya

Verifying custom AI chips for Microsoft Artificial Intelligence team

▪ Project: AISoC (Artificial Intelligence System on Chip) team

▪ Driving and leading Stub based verification at SoC level by replacing actual IP/Sub system with stubs to generate more randomize traffic to verify fabrics and memories.

▪ Worked on writing stub based rtl with traffic generator, handling the whole flow at SoC level to generate the traffic and find bugs at fabrics at early stage in production design life cycle.

▪ Worked on creating testplan generation, reviewing it, writing test ymls and C based tests at SoC level to deliver bug free design.

▪ Gained the knowledge on Generative AI, LLMs, RAG to help improve productivity at individual level.

▪ Guided many team members and helped the AI team to grow exponentially by taking many interviews and created diversity and inclusive culture.

▪ Skills: SystemVerilog, UVM verification methodology, Unix, IP Verification

▪ Project: GPU Memory Subsystem division

▪ Worked on unit/IP level verification in arbitration IP presents in GPU memory subsystem.

▪ Worked on performance verification and VIP integration in the same IP for next gen GPU.

▪ Project: Next Gen IPUs (Intel Infrastructure Processing Unit) (SmartNIC)
▪ Reference model component development for out-of-order packet flit received from AXI4 stream and
end to end scoreboard of packets
▪ Experience in leading packet processing IP verification and class of service queue IP verification from testplan development to coverage closure
▪ Single-handed drove TFM (Tool Flow Methodology) related activities at multiple IP.
▪ Developed Perl script for generating directed regression test suite for functional verification of packet processing IP.
▪ Trained multiple interns joined the team with SystemVerilog, UVM methodology and functional verification.
▪ Successfully lead and completed packet processing IP level Unit and features verification from architecture understanding, testplan creation, environment infrastructure update, testbench component development, test scenario and sequence creation, checkers, test running and debugging with designers or at subsystem level, regression, triage and coverage closure
▪ Having experience in networking ethernet protocol and AMBA AXI4, APB communication protocol.
▪ Hands on experience with verification tools such as VCS, Verdi waveform analyzer and third-party VIP integration (such as Synopsys VIPs).
▪ Expertise in constraint random function verification and Performance-QoS verification of multiple IPs in SystemVerilog and UVM based testbench environment